The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a guard ring.
In the art of semiconductor devices, a so-called multilayer interconnection structure is used for interconnecting various semiconductor elements formed on a common substrate. A multilayer interconnection structure includes a number of interlayer insulation films provided on the common substrate for covering the semiconductor elements, wherein the interlayer insulation films carry an interconnection pattern in such a manner that the interconnection pattern are embedded in the interlayer insulation films.
In such semiconductor devices that use the multilayer interconnection structure, it is generally practiced to provide a guard ring structure along an outer periphery of the semiconductor substrate so as to block the penetration of moisture or corrosive gas into the interior of the semiconductor device along the interface between the interlayer insulation films.
FIG. 1A shows a typical conventional guard ring in an enlarged view, while FIG. 1B shows the overall construction of the guard ring of FIG. 1A in a plan view.
Referring to FIGS. 1A and 1B, it can be seen that a guard ring structure 12 is formed along an outer periphery of the semiconductor chip on which a semiconductor device 11 is formed, in such a manner that the guard ring structure 12 surrounds the semiconductor device 11 continuously.
FIG. 2 shows a cross-sectional view of the structure of FIG. 1B taken along a line 2–2′.
Referring to FIG. 2, the semiconductor device 11 is formed on a Si substrate 21 formed with a field oxide film 22, wherein the field oxide film 22 defines a diffusion region 21A on the surface of the Si substrate 21.
On the Si substrate 21, it should be noted that interlayer insulation films 23–25 are deposited consecutively so as to cover the field oxide film 22 and the diffusion region 21A, wherein the interlayer insulation films 22–25 may be formed of an inorganic material such as SiO2, PSG, BPSG, and the like. Alternatively, the interlayer insulation films may be formed of an organic material such as fluorocarbon, hydrocarbon, polyimide, or organic SOG.
As represented in FIG. 2, the interlayer insulation film 23 is formed of a contact groove 23A exposing the diffusion region 21A, such that the contact groove 23A extends continuously along the outer periphery of the semiconductor device 11. The contact groove 23A is filled with a conductive wall 23B of W, and the like, and a conductive pattern 24A of W, WSi or polysilicon is formed on the interlayer insulation film 23 in mechanical as well as electrical contact with the conductive wall 23B. Thereby, the conductive pattern 24A extends along the outer peripheral edge of the semiconductor device 11.
The conductive pattern 24A thus formed, in turn, is covered by the interlayer insulation film 24, wherein the interlayer insulation film 24 is formed with a contact groove 24B so as to expose the conductive pattern 24A. Thereby, the contact groove 24B extends continuously and in parallel with the contact groove 24A along the outer periphery of the semiconductor device 11.
The contact groove 24B is filled with a conductive wall 24C of W, and the like, and a conductive pattern 25A of W, WSi or polysilicon is formed on the interlayer insulation film 24 in electrical as well as mechanical contact with the conductive wall 24C. Thereby, the conductive pattern 25A extends along the outer periphery of the semiconductor device in correspondence to the contact groove 24B.
The conductive pattern 25A, in turn, is covered by the interlayer insulation film 25 and a contact groove 25B is formed in the interlayer insulation film 25 continuously along the outer periphery of the semiconductor device 11 in a parallel relationship with respect to the conduct groove 24B, wherein the contact groove 25B is formed so as to expose the conductive pattern 25A.
Further, the contact groove 25B is filled with a conductive wall 25C and a conductive pattern 26A of W, WSi or polysilicon is formed on the interlayer insulation film 25 in electrical as well as mechanical contact with the conductive groove 25C, wherein the conductive pattern 26A is formed continuously along the outer periphery of the semiconductor device 11 in correspondence to the contact groove 25B. The conductive pattern 26A is covered by a protective film 26 such as SiN formed on the interlayer insulation film 25.
According to the construction of FIG. 2, the conductive walls 23B, 24C and 25C form, together with the conductive patterns 24A, 25A and 26A, the guard ring 12 represented in FIG. 1B. By forming such a guard ring 12, the problem of penetration of H2O or corrosive gas into the interior of the semiconductor device 11 along the interface boundary between the interlayer insulation films, such as the interface between the interlayer insulation film 23 and the interlayer insulation film 24, is effectively blocked.
Conventionally, the guard ring structure such as the one represented in FIG. 2 has been formed simultaneously to the formation of the multilayer interconnection structure. In such conventional multilayer interconnection structure, it has been practiced to form a conductive pattern on an underlying layer and cover the conductive pattern thus formed by an insulation film. The insulation film thus formed is further subjected to a planarization process.
In recent advanced semiconductor devices called sub-micron devices or sub-quarter-micron devices, on the other hand, delay of electric signals in the multilayer interconnection structure is becoming a serious problem. Thus, in order to address the foregoing problem of signal delay, it has been practiced to use low-resistance Cu for the conductive pattern in such a multilayer interconnection structure in combination with organic interlayer insulation films, which have a characteristically low dielectric constant.
In the multilayer interconnection structure using Cu for the interconnection pattern, it has been practiced to use a so-called dual-damascene process in view of the fact that patterning of Cu by a dry etching process is difficult, contrary to the conventional conductor material such as Al, W, Si or Au used for this purpose. In a dual-damascene process, interconnection grooves or contact holes are formed in the interlayer insulation film in advance and the interconnection grooves or contact holes are filled with a Cu layer by way of a suitable deposition process such as an electrolytic plating process. After the deposition of the Cu layer, the part of the Cu layer remaining on the interlayer insulation film is removed by a chemical mechanical polishing (CMP) process. As a result of the CMP process, a Cu pattern of Cu plug filling the interconnection groove or contact hole is obtained.
In view of the potential usefulness of forming extremely minute patterns, dual-damascene process is used not only in the multilayer interconnection structure that uses Cu for the interconnection patterns but also in general multilayer interconnection structure for use in advanced, highly miniaturized semiconductor devices. Further, CMP process can provide an exactly flat surface and is used extensively in various planarizing processes.
FIG. 3A shows a CMP process conducted to the semiconductor device 11 represented in FIGS. 1A and 1B, while FIG. 3B shows a part of FIG. 3A in an enlarged view.
Referring to FIGS. 3A and 3B, the CMP process is conducted on a rotating polishing platen covered with a polishing cloth, and a semiconductor wafer 10, on which a number of semiconductor devices are formed, is urged against the polishing cloth under a predetermined pressure while dropping a polishing slurry. As the same time, the semiconductor wafer 10 itself is also rotated at a predetermined speed.
When such a CMP process is applied to the semiconductor device 11 having the guard ring structure, it will be understood from FIG. 3B that there is a moment in which the direction of the CMP coincides with the elongating direction of the guard ring structure 12.
FIG. 4 shows the relative distribution of the velocity of slurry particles for the case in which the wafer 10 of FIG. 3A is urged against the polishing platen rotating at the rotational speed of 0.857 rps (rotation per second) while rotating the wafer 10 at the rotational speed of 0.857 rps.
Referring to FIG. 4, it will be noted that the velocity vx and the velocity vy of the polishing particles change, when the particles are on the central part of the wafer 10, along a circular path represented by a shading as a result of the rotation or revolution of the wafer 10. On the other hand, the velocities vx and vy of the slurry particles on the peripheral part of the wafer 10 change along a circular path represented in FIG. 4 by a continuous line. It should be noted that the x-direction and y-direction are defined for the two-dimensional Cartesian coordinate system fixed to the wafer 10.
As can be seen clearly from FIG. 4, the relative speed of the abrasive particles becomes larger in the peripheral part of the wafer 10 than in the central part due to the effect of increased distance from the rotational center of the rotating platen. This effect of increased relative speed of the abrasive particles at the peripheral part of the wafer 10 is enhanced when the diameter of the wafer 10 is increased.
Referring back to FIGS. 3A and 3B, it should be noted that the guard ring 12 on the wafer 10 experience a large stress at the time of the CMP process as a result of the engagement with the slurry particles, wherein the effect of the stress is enhanced in the semiconductor devices 11 that are formed on the peripheral part of the wafer 10 than in the semiconductor devices 11 formed on the central part.
In the state of FIG. 3B, it can be seen that the abrasive particles exert a stress in the elongating direction of the guard ring structure 12. In view of the fact that such a long continuous pattern generally includes, somewhere therein, a defective part where the adhesion to the underlying layer is poor, there is a substantial risk, in the state of FIG. 3B, that an exfoliation of the guard ring 12 may occur in such a defective part when the elongating direction of the guard ring 12 is coincident with the moving direction of the polishing particles. In the case the elongating direction of the guard ring 12 is oblique to the direction of the moving polishing particles, on the other hand, the guard ring 12 is laterally supported by the walls of the groove in which the guard ring 12 is formed, and no substantial exfoliation occurs even in the defective part. Further, such a problem of conductive pattern exfoliation associated with the CMP process does not occur in the interconnection patterns in the multilayer interconnection structure in view of the fact that such an interconnection pattern generally has a zigzag or complex pattern.
In the state of FIG. 3B, the guard ring 12 extending in the y-direction lacks such a lateral support structure, and thus, the existence of defective part in any of the conductive walls 23B, 24C or 25C easily causes damaging in the guard ring 12 in correspondence to such a defective part as represented in FIG. 5. In FIG. 5, it should be noted that those parts corresponding to the parts described previously ar5e designated by the same reference numerals and the description thereof will be omitted. In the structure of FIG. 5, it will be noted that the bottom surface and the side wall of the contact groove 23A is covered by an adhesion film (23B)1 of a refractory metal compound such as TiN for improving the adhesion.